ye question the us me

If a DRAM has 512 rows and its fresh time is 8ms .What should e the frequency of row refresh operation on the average?(5)

Reset defination or types (5)

Consider a 64KB directed mapped cache with a line length of 32 bytes. Determine the number of bits in the address that refers to the byte within a cache line. (5)

: Does DMA affect the relationship b/w the memory system and CPU? Explain with reasons. (5)

best of luck for ur paper

3 feb 2012 (4:30pm)

Final term current ppr

40 mcqs

41.

What are the functions of memory cell? 2 marks

Sol:

A memory cell provides four functions: Select, DataIn, DataOut, and Read/Write. DataIn

means input and DataOut means output. The select signal would be enabled to get an

operation of Read/Write from this cell.

42.

What is Packet Switching? 2 marks

Sol:

This is a method of breaking data files into small packets or chunks in order to send them across a network.

43.

How we can specify registers in RTL? Give an example? 2 marks

Sol:

Specifying Registers

The format used to specify registers is

For example, IR<31..0> means bits numbered 31 to 0 of a 32-bit register named “IR”

(Instruction Register).

44.

What is seek time of hard disk? 3 marks

Sol:

When hard disk is required to read data from a particular location of the disk, the head moves

towards the selected track and this process is called seek..

The time required to seek a particular track is defined by the manufacturer. Maximum,

minimum and average seek times are specified. Seek time depends upon the present

position of the head and the position of the required sector. For the sake of calculations,

we will use the average value of the seek time.

45.

Differences between RAID2 and RAID 3? 3 marks

Sol:

• In RAID 2, error-correcting code is calculated across corresponding bits on each

data disk.

• RAID 3 requires only a single redundant disk.

• Instead of an error-correcting code, a simple parity bit is computed for the set of

individual bits in RAID 3

46.

What are three main functions of control Unit? 3marks

Sol:

The control unit is responsible for generating control signals
Responsible for generating timing signals.
It is responsible for synchronization of internal and external events.

47.

Difference between Spatial Locality and Temporal Correlation? 3 marks

Sol:

Spatial Locality

This would mean that in a part of a program, if we have a particular address being

accessed then it is highly probable that the data available at the next address would be

highly accessed.

Temporal Correlation

In this case, we say that at a particular time, if we have utilized a particular part of the

memory then we might access the adjacent parts very soon.

48.

How shift instruction are useful? When we use them? 3 marks

Sol:

Using shift instructions (shiftl, asr, etc.) is faster that mul and div, if the

multiplier or divisor is a power of 2.

Shift for such arithmetic operations are more efficient than the corresponding arithmetic instruction.

Shift Instructions.

Right shift, left shift & arithmetic right shift.

49.

Assume there is an accumulator based machine in which there are eight general purpose registers of the CPU. Each register is 16-bits in length. Also there are two additional 16-bit system registers which are the program counter (PC) and the instruction register (IR). The size of the memory word is 16-bit.

Using yours knowledge of processor design process, answer the following question.

a) Which name convention will you use to name each of these eight general purpose registers?

b) What is the available memory space size knowing that memory word is 16 bits. 5 marks

Sol:

a) As the length of register is 16-bit so we use Little-endian name convention

b) memory word is 16-bit so the available memory space size is 2¹⁶ bytes

50.

Find the bandwidth of a memory system that has a latency of 30ns, a pre charge time of 10ns and transfers 3 bytes of data per access. 5 marks

Sol:

Time between two memory reference

= latency + pre charge time

=30ns+10ns

= 40ns

Throughput = 1/40ns

=0.025 operation/sec

Bandwidth= 3*0.025

=0.075 byets/sec

51.

Using radix conversion algorithm converts 392₁₀ to base 16. 5 marks

Sol:

392/16=24 (rem=8), x0=8

24/16=1(rem=8), x1=8,x2=1

Thus 392₁₀= 188₁₆

52.

5 marks

CS501 Final Term Paper Fall 2011 (Subjective)

03-02-2012

1. Diff b/w internal fragmentation and external fragmentation. (5)

2. An IO system with single disk gets 100 IO requests/sec. Assume the average time for a disk to service an IO request is 6ms. What is utilization of the IO system? (5)

3. What are characteristics of D-flip-flop? Draw truth table. (5)

4. Does DMA affect the relationship b/w the memory system and CPU? Explain with reasons. (5)

5. Diff b/w sender and receiver overhead related to network. (3)

6. What are functions of valid bit in Associative mapping strategy for cache? (3)

7. Recode the integer 484 according to booth procedure. (3)

8. Write structural RTL of ret ra. (3)

9. Consider a 64KB directed mapped cache with a line length of 32 bytes. Determine the number of bits in the address that refers to the byte within a cache line. (2)

10. What attributes should a device have in order to be qualified as a master device? (2)

11. What functions are provided by a typical memory cell? (2)

12. What is format of 2-address instruction set? (2)

Read more: CS501 Current Final Term Papers Fall 2011 ( 03 Feb to 16 Feb 2012 ) - Virtual University of Pakistan http://vustudents.ning.com/group/cs501advancecomputerarchitecture/forum/topics/cs501-current-final-term-papers-fall-2011-03-feb-to-16-feb-2012#ixzz1m4GxewW5

Current paper with solution

What function is performed by the reset operation of a processor? What are the

two types of reset operations?
Answer:
Reset operation is required to change the processor‘s state to a known, defined value.
The two essential features of a reset instruction are clearing the control step counter and
reloading the PC to a predefined value.
Hard Reset
The SRC performs a hard reset upon receiving a start (Strt) signal. This initializes the PC
and the general registers.
Soft Reset
The SRC performs a soft reset upon receiving a reset (rst) signal. The soft reset results in
initialization of PC only.
Q2 What do you know about Hard disk.
Solution A hard disk drive (HDD; also hard drive, hard disk, or disk drive)[2] is a device
for storing and retrieving digital information, primarily computer data. It consists of one
or more rigid (hence "hard") rapidly rotating discs (often referred to as platters), coated
with magnetic material and with magnetic heads arranged to write data to the surfaces
and read it from them.
Hard drives are classified as non-volatile, random access, digital, magnetic, data storage
devices. Introduced by IBM in 1956, hard disk drives have decreased in cost and physical
size over the years while dramatically increasing in capacity and speed.
Hard disk drives have been the dominant device for secondary storage of data in general
purpose computers since the early 1960s.[3] They have maintained this position because
advances in their recording capacity, cost, reliability, and speed have kept pace with the
requirements for secondary storage.[3]
Q 3
(0.23) 10 convert in base 2
Question no 4 What is meant by Packet switching
Ans lecture no 34 …(page no360)

Qusetion no 6
Classification of fiber optics mode multimode and mono mode?
Solution
Multimode…… this fiber has large diameter when light is injected,it is disperses,so the effective data rate is dicreses.
Mono mode
Its diameter is very small.So dispersion ios small and data rate is very high.
Question no 7
Considered a 64kb direct maped catch with a line length of 32bytes
a determine the number of bits in the address that refer to the byte withen a cache line.
b determine the number of bits in the address required to select the cache line.
Solution (lecture no 41 ) page 348 o
Question no 8
If a DRAM has 512 rows and its fresh time is 9ms .What shoul be the frequency of rowrefresh operation on the average?
Solution
Refresh time =9ms
Number of rows =512
Therefore we have to do 512 rows refresh operation in 9ms interval.in other words one rowrefresh operation every( 9*10-³)/512=1.76*10 second
Question
Structural RTL for not instruction not ra ,rb
Solution in lecture no 13
Question why we use matrix in decoder
I dont know
Msqs were from mostly past papers

Read more: CS501 Current Final Term Papers Fall 2011 ( 03 Feb to 16 Feb 2012 ) - Virtual University of Pakistan http://vustudents.ning.com/group/cs501advancecomputerarchitecture/forum/topics/cs501-current-final-term-papers-fall-2011-03-feb-to-16-feb-2012#ixzz1m4H1mfkv

CS501 Final Term Paper Fall 2011 (Subjective)

03-02-2012

1. Diff b/w internal fragmentation and external fragmentation. (5)

2. An IO system with single disk gets 100 IO requests/sec. Assume the average time for a disk to service an IO request is 6ms. What is utilization of the IO system? (5)

3. What are characteristics of D-flip-flop? Draw truth table. (5)

4. Does DMA affect the relationship b/w the memory system and CPU? Explain with reasons. (5)

5. Diff b/w sender and receiver overhead related to network. (3)

6. What are functions of valid bit in Associative mapping strategy for cache? (3)

7. Recode the integer 484 according to booth procedure. (3)

8. Write structural RTL of ret ra. (3)

9. Consider a 64KB directed mapped cache with a line length of 32 bytes. Determine the number of bits in the address that refers to the byte within a cache line. (2)

10. What attributes should a device have in order to be qualified as a master device? (2)

11. What functions are provided by a typical memory cell? (2)

12. What is format of 2-address instruction set? (2)

Current Final Term Paper Exam 2012

Saturday, February 11, 2012

CS501 Current Final Term Papers Fall 2011 ( 03 Feb to 16 Feb 2012 )

What is Packet Switching? 2 marks

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